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Clock-domain and reset verification in the low-power design era

SoCs integrate components from many sources. Accompanying this abundance of features is significant complexity that needs to be correctly handled. One source of complexity is that multiple components...

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X propagation

Hardware description languages such as SystemVerilog use the symbol ‘X’ to describe any unknown logic value. If a simulator is unable to decide whether a logic value should be a ‘1’, ‘0’, or ‘Z’ for...

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Spot the difference between false and real clock violations

Clock domain crossings (CDCs) are a major source of complex SoC design errors that can and do easily slip past conventional verification tools and make their way into silicon. Thus it is essential to...

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Reset optimization pays big dividends before simulation

Reset optimization is another one of those design issues that has leapt in complexity and importance as we have moved to ever more complex system-on-chips. Like clock domain crossing, it is one that we...

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Exploiting the power of reset in formal verification

The reset state of a module or SoC that is being verified can have a huge impact on the scope and correctness of the verification. When using simulation for verification, the reset phase is usually not...

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